1. Field of the Invention
The present invention relates to an ESD protection apparatus for an electrical device.
2. Description of the Related Art
In microelectronics, more and more integrated circuits with low structure widths are utilized. These lower structure widths enable higher clock rates of the integrated circuits and thus higher data rates of the signals at the pins of the integrated circuits. In order to enable a communication between two electrical devices, which is as interference-free as possible, it is required to make the leading and falling edges of the transmitted bits as steep as possible. Therefore, it is required to keep the capacitive loads at the inputs and outputs of an integrated circuit as low as possible. These capacities do lead to a flattening of the curves of the current and voltage flows at the inputs and outputs of the integrated circuit.
An integrity of the signal in modern integrated circuits depends mainly on the input capacitance of the input and output stages. Thus, these modern integrated circuits operate with bit rates in the range of several Gigahertz. The input signal slew-rate and an ISI (intersymbol interreference), respectively, of the signal is influenced largely by the input capacitance of the input and output stages.
The capacitances of the inputs and outputs consist of a capacitance of the off-chip driver elements, an input capacitance of the chip, a package capacitance and a capacitance of an ESD protection structure (ESD=Electro Static Discharge). The proportion of the capacitance of the ESD structure, is up to 30% of the overall capacitance of the input and output stages and even up to 70% of the input stage of only input pins.
Integrated circuits have to survive a connection charged with up to 1000 V or more than 100 pF capacitance of human body or an assembling machinery. Diodes or any other kind of protection devices, which are used for such protection must be relatively large.
To allow an increase of the bit rate of memory data or command address buses or other chip-to-chip or board-to-board data transmission systems, the capacitance of the diodes, which are used for protection from overvoltages, should be kept as low as possible. This is typically accompanied with reduction of the area of the diode, which is used as ESD protection structure.
The ESD protection structure present on the chip and its capacitance stand thus in the way of increasing the data rate of a signal on a data bus, which is connected to a pin and to several pins, respectively, of a chip.
FIG. 3 explains the cross-section structure of an exemplary BGA (BGA=Ball Grid Array) package. The chip 11, a package substrate 21, traces 31, solder balls 41, bonding wires 51 and the chip pads 61 are illustrated.
The chip 11 is deposited on the package substrate 21. The traces 31 are deposited on the surface of the package substrate 21 opposite to the chip 11, whereon again the solder balls 41 are disposed. The chip pads 61, which are electrically connected to the traces 31 via the bond wires 51, are attached to the chip 11.
By the structure shown in FIG. 3, an electrically conductive connection is established between the solder balls 41 and the chip pads 61. Thereby, the solder balls 41 are electrically conductively connected to the trace 31, which is again electrically conductively connected to the chip pads 61 via the bonding wires 51. Via the structure shown in FIG. 3, electrical signals originating from a circuit board not shown here and transmitted by the same to the solder ball 41 are transmitted from there to the chip pads 61. The connection between chip pad 61 and solder ball 41 is thus part of a signal path, which, for example, a signal passes between the chip 11 and an adjacent chip not shown here.
Typically, an ESD protection diode or a plurality of ESD protection diodes is attached in between the chip I/O pad 61, and internal chip supply wires like a GND and a VDD for example in order to protect the chip 11 from electrical overloads. This capacitance of the ESD protection diode not shown here leads to a flattening of the preferably short rise/fall edges of the binary signal applied to the chip pad 61. This flattening becomes greater the greater the capacitance of the ESD protection diode. The same is also applicable to any kind of high frequency analog signals. Any capacitance acts like a low-pass filter for high frequency harmonics of the signal. The capacitance of the ESD protection diode is thus in the way of increasing the data rate of a signal at the chip pad 61.